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sram as5ss128k36 austin semiconductor, inc. as5ss128k36 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 128k x 36 ssram synchronous zbl sram flow-thru output features ? high frequency and 100% bus utilization ? fast cycle times: 11ns & 12ns ? single +3.3v +5% power supply (v dd ) ? advanced control logic for minimum control signal interface ? individual byte write controls may be tied low ? single r/w\ (read/write) control pin ? cke\ pin to enable clock and suspend operations ? three chip enables for simple depth expansion ? clock-controlled and registered addresses, data i/os and control signals ? internally self-timed, fully coherent write ? internally self-timed, registered outputs to eliminate the need to control oe\ ? snooze mode for reduced-power standby ? common data inputs and data outputs ? linear or interleaved burst modes ? burst feature (optional) ? pin/function compatibility with 2mb, 8mb, and 16mb zbl sram ? automatic power-down options marking ? timing (access/cycle/mhz) 8.5ns/11ns/90 mhz -11 9ns/12ns/83 mhz -12 ? packages 100-pin tqfp dq no. 1001 ? operating temperature ranges military (-55 o c to +125 o c) xt industrial (-40 o c to +85 o c) it general description the austin semiconductor, inc. zero bus latency sram family employs high-speed, low-power cmos designs using an ad- vanced cmos process. asis 4mb zbl srams integrate a 128k x 36 sram core with advanced synchronous peripheral circuitry and a 2-bit burst counter. these srams are optimized for 100 percent bus utilization, eliminating any turnaround cycles for read to write, or write to read, transitions. all synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (clk). the synchronous inputs include all addresses, all data inputs, chip enable (ce\), two additional chip enables for easy depth expansion (ce2, ce2\), cycle start input (adv/ld\), synchronous clock enable (cke\), byte write enables (bwa\, bwb\, bwc\, and bwd\) and read/write (r/ w\). asynchronous inputs include the output enable (oe\, which may be tied low for control signal minimization), clock (clk) and snooze enable (zz, which may be tied low if unused). there is also a burst mode pin (mode) that selects between interleaved and linear burst modes. mode may be tied high, low or left unconnected if burst is unused. the flow-through data-out (q) is enabled by oe\. write cycles can be from one to four bytes wide as controlled by the write control inputs. all read, write and deselect cycles are initiated by the adv/ld\ input. subsequent burst addresses can be internally generated as controlled by the burst advance pin (adv/ld\). use of burst mode is optional. it is allowable to give an address for each individual read and write cycle. burst cycles wrap around after the fourth access from a base address. to allow for continuous, 100 percent use of the data bus, the flow-through zbl sram uses a late write cycle. for ex- ample, if a write cycle begins in clock cycle one, the address is present on rising edge one. byte writes need to be asserted on the same cycle as the address. the write data associated with the address is required one cycle later, or on the rising edge of clock cycle two. address and write control are registered on-chip to simplify write cycles. this allows self-timed write cycles. individual byte enables allow individual bytes to be written. during a byte write cycle, bwa\ controls dqa pins; bwb\ controls dqb pins; bwc\ controls dqc pins; and bwd\ controls dqd pins. cycle types can only be defined when an address is loaded, i.e., when adv/ld\ is low. parity/ecc bits are available on this device. austins 4mb zbl srams operate from a +3.3v v dd power supply, and all inputs and outputs are lvttl-compatible. the device is ideally suited for systems requiring high bandwidth and zero bus turnaround delays. for more products and information please visit our web site at www.austinsemiconductor.com
sram as5ss128k36 austin semiconductor, inc. as5ss128k36 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 pin assignment (top view) 100-pin tqfp (dq) pin descriptions tqfp pins symbol type description 37 36 32-35, 44-50, 81, 82, 99, 100 sa0 sa1 sa input synchronous address inputs: these inputs are registered and must meet the setup and hold times around the rising edge of clk. pins 83 and 84 are reserved as address bits for the higher-density 8mb and 16mb zbl srams, respectively. sa0 and sa1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. 93 94 95 96 bwa\ bwb\ bwc\ bwd\ input synchronous byte write enables: these active low inputs allow individual bytes to be written when a write cycle is active and must meet the setup and hold times around the rising edge of clk. byte writes need to be asserted on the same cycle as the address. bwa\ controls dqa pins; bwb\ controls dqb pins; bwc\ controls dqc pins; bwd\ controls dqd pins. 87 cke\ input synchronous clock enable: this active low input permits clk to propagate throughout the device. when cke is high, the device ignores the clk input and effectively internally extends the previous clk cycle. this input must meet setup and hold times around the rising edge of clk. 88 r/w\ input read/write: this input determines the cycle type when adv/ld\ is low and is the only means for determining reads and writes. read cycles may not be converted into writes (and vice versa) other than by loading a new address. a low on this pin permits byte write operations and must meet the setup and hold times around the rising edge of clk. full bus-width writes occur if all byte write enables are low. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 dqc dqc dqc v dd q v ss dqc dqc dqc dqc v ss v dd q dqc dqc v ss v dd v dd v ss dqd dqd v dd q v ss dqd dqd dqd dqd v ss v dd q dqd dqd dqd dqb dqb dqb v dd q v ss dqb dqb dqb dqb v ss v dd q dqb dqb v ss v ss v dd zz dqa dqa v dd q v ss dqa dqa dqa dqa v ss v dd q dqa dqa dqa mode (lbo\) sa sa sa sa sa1 sa0 dnu dnu v ss v dd dnu dnu sa sa sa sa sa sa sa sa sa ce\ ce2 bwd\ bwc\ bwb\ bwa\ ce2\ v dd v ss clk r/w\ cke\ oe\ (g\) adv/ld\ nf nf sa sa
sram as5ss128k36 austin semiconductor, inc. as5ss128k36 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 pin descriptions (continued) tqfp pins symbol type description 64 zz input snooze enable: this active high, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. when zz is active, all other inputs are ignored. 89 clk input clock: this signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clock's rising edge. 98, 92 ce\, ce2\ input synchronous chip enable: these active low inputs are used to enable the device and are sampled only when a new external address is loaded (adv/ld\ low). ce2\ can be used for memory depth expansion. 97 ce2 input synchronous enable: this active high input is used to enable the device and is sampled only when a new external address is loaded (adv/ld\ low). this input can be used for memory depth expansion. 86 oe\ (g\) input output enable: this active low, asynchronous inputs enables the data i/o output drivers. g\ is the jedec-standard term for oe\. 85 adv/ld\ input synchronous address advance/load: when high, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. when adv/ld\ is high, r/w\ is ignored. a low on adv/ld\ clocks a new address at the clk rising edge. 31 mode (lbo\) input mode: this inputs selects the burst sequence. a low on this pin selects linear burst. nc or high on this pin selects interleaved burst. do not alter input state while device is operating. lbo\ is the jedec-standard term for mode. (a) 51, 52, 53, 56-59, 62, 63 (b) 68, 69, 72-75, 78, 79, 80 (c)1, 2, 3, 6-9, 12, 13 (d) 18, 19, 22-25, 28, 29, 30 dqa dqb dqc dqd input/output sram data i/os: byte "a" is dqa pins; byte "b" is dqb pins; byte "c" is dqc pins; byte "d" is dqd pins. input data must meet setup and hold times around the rising edge clk. 15, 16, 41, 65, 91 v dd supply power supply: see dc electrical characteristics and operating conditions for range. 5, 10, 14, 17, 21, 26 40, 55, 60, 66, 67, 71 76, 90 vss ground ground: gnd 4, 11, 20, 27, 54, 61 70, 77 v dd q supply isolated output buffer supply: see dc electrical characteristics and operating conditions for range. 38, 39, 42, 43, 83, 84 64 nc ---- no connect: these pins can be left floating or connected to gnd to minimize thermal impedance. 38, 39, 42, 43 dnu ---- do not use: these signals may with be unconnected or wired to gnd to minimize thermal impedance. 83, 84 nf ---- no function: these pins are internally connected to the die and will have the capacitance of an input pin. it is allowable to leave these pins unconnected or driven by signals. pins 83 and 84 are reserved for address expansion.
sram as5ss128k36 austin semiconductor, inc. as5ss128k36 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 first address (external) second address (internal) third address (internal) fourth address (internal) x...x00 x...x01 x...x10 x...x11 x...x01 x...x00 x...x11 x...x10 x...x10 x...x11 x...x00 x...x01 x...x11 x...x10 x...x01 x...x00 first address (external) second address (internal) third address (internal) fourth address (internal) x...x00 x...x01 x...x10 x...x11 x...x01 x...x10 x...x11 x...x00 x...x10 x...x11 x...x00 x...x01 x...x11 x...x00 x...x01 x...x10 interleaved burst address table (mode = nc or high) linear burst address table (mode = low) partial truth table for read/write commands* function r/w\ bwa\ bwb\ bwc\ bwd\ read h xxxx write abort/nop l hhhh write byte a (dqa, dqpa) 2 l lhhh write byte b (dqb, dqpb) 2 lhlhh write byte c (dqc, dqpc) 2 lhhlh write byte d (dqd, dqpd) 2 lhhhl write all bytes lllll * note: using r/w\ and byte write(s), any one or more bytes may be written.
sram as5ss128k36 austin semiconductor, inc. as5ss128k36 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 functional block diagram note: the functional block diagram illustrates simplified device operation. see truth table, pin descriptions and timing diagrams for detailed information. 17 17 15 17 sa0, sa1, sa sa1' sa0' mode adv/ld\ clk k cke\ 17 adv/ld\ bwa\ bwb\ dqs bwc\ bwd\ r/w\ oe\ ce\ ce2 ce2\ o u t p u t b u f f e r s d a t a s t e e r i n g s e n s e a m p s 128k x 9 x 4 memory array write drivers write registry and data coherency control logic read logic input register write address register address register burst logic d1 d0 q1 q0 sa1 sa0 k ce e e 17
sram as5ss128k36 austin semiconductor, inc. as5ss128k36 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 state diagram for zbl sram ds ds write read read burst burst write begin read burst read begin write burst write burst read burst burst write ds deselect write read write read ds ds key: command action ds deselect read new read write new write burst burst read, burst write or continue deselect note: 1. a stall or ignore clock edge cycle is not shown in the above diagram. this is because cke\ high only blocks the clock (clk) input and does not change the state of the device. 2. states change on the rising edge of the clock (clk).
sram as5ss128k36 austin semiconductor, inc. as5ss128k36 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 truth table (5-10 ) note: 1. continue burst cycles, whether read or write, use the same control inputs. the type of cycle performed (read or write) is chosen in the initial begin burst cycle. a continue deselect cycle can only be entered if a deselect cycle is first executed. 2. dummy read and write abort cycles can be considered nops because the device performs no external operation. a write abort means a write command is given, but no operation is performed. 3. oe\ may be wired low to minimize the number of control signals to the sram. the device will automatically turn off the output drivers during a write cycle. oe\ may be used when the bus turn-on and turn-off times do not meet an applications requirements. 4. if an ignore clock edge command occurs during a read operation, the dq bus will remain active (low-z). if it occurs during a write cycle, the bus will remain in high-z. no write operations will be performed during the ignore clock edge cycle. 5. x means dont care. h means logic high. l means logic low. bwx = h means all byte write signals (bwa\, bwb\, bwc\, bwd\) are high. bwx = l means all byte write signals are low. 6. bwa\ enables writes to byte a (dqa pins); bwb\ enables writes to byte b (dqb pins); bwc\ enables writes to byte c (dqc pins); bwd\ enables writes to byte d (dqd pins). 7. all inputs except oe\ and zz must meet setup and hold times around the rising edge (low to high) of clk. 8. wait states are inserted by setting cke\ high. 9. this device contains circuitry that will ensure that the outputs will be in the high-z during power-up. 10. the device incorporates a 2-bit burst counter. address wraps to the initial address every fourth burst cycle. 11. the address counter is incremented for all continue burst cycles. operation address used ce\ ce2\ ce2 zz adv/ld\ r/w\ bwx oe\ cke\ clk dq notes deselect cycle none h x x l l x x x l l h high-z deselect cycle none x h x l l x x x l l h high-z deselect cycle none x x l l l x x x l l h high-z continue deselect cycle none x x x l h x x x l l h high-z 1 read cycle (begin burst) external l l h l l h x l l l hq read cycle (continue burst) next x x x l h x x l l l h q 1, 11 nop/dummy read (begin burst) external l l h l l h x h l l h high-z 2 dummy read (continue burst) next x x x l h x x h l l h high-z 1, 2, 11 write cycle (begin burst) external l l h l l l l x l l hd 3 write cycle (continue burst) next x x x l h x l x l l h d 1, 3, 11 nop/write abort (begin burst) none l l h l l l h x l l h high-z 2, 3 write abort (continue burst) next x x x l h x h x l l h high-z 1, 2, 3, 11 ignore clock edge (stall) current x x x l x x x x h l h --- 4 snooze mode none x x x h x x x x x x high-z
sram as5ss128k36 austin semiconductor, inc. as5ss128k36 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 absolute maximum ratings* voltage on v dd supply relative to v ss .................-0.5v to +4.6v voltage on v dd q supply relative to v ss .................-0.5v to v dd v in .................................................................. -0.5v to v dd q +0.5v storage temperature (plastics) ..........................-55 c to +150 c short circuit output current ..........................................100ma max. junction temperature*.............................................+150 c *stresses greater than those listed under "absolute maximum rat- ings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this speci- fication is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect reliability. **junction temperature depends upon package type, cycle time, load- ing, ambient temperture and airflow. dc electrical characteristics and recommended operating conditions (-55 o c < t a < +125 o c; v dd, v dd q = +3.3v +0.165v unless otherwise noted) note: 1. all voltages referenced to v ss (gnd). 2. overshoot: v ih < +4.6v for t < t khkh /2 for i < 20ma. undershoot: v il < -0.7v for t < t khkh /2 for i < 20ma. power-up: v ih < +3.465v and v dd < 3.135v for t < 200ms. 3. mode pin has an internal pull-up, and input leakage = + 10 m a. 4. the load used for v oh , v ol testing is shown in figure 2. ac load current is higher than the shown dc values. ac i/o curvers are available upon request. 5. v dd q should never exceed v dd . v dd and v dd q should be externally wired together to the same power supply. 6. this parameter is sampled. description conditions symbol min max units notes input high (logic 1) voltage v ih 2.0 v dd + 0.3 v 1, 2 input high (logic 1) voltage dq pins v ih 2.0 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.8 v 1, 2 input leakage current 0v < v in < v dd il i -1.0 1.0 m a3 output leakage current output(s) disabled, 0v < v in < v dd il o -1.0 1.0 m a output high voltage i oh = -4.0ma v oh 2.4 --- v 1, 4 output low voltage i ol = 8.0ma v ol --- 0.4 v 1, 4 supply voltage v dd 3.135 3.465 v 1 isolated output buffer supply v dd q 3.135 v dd v 1, 5 capacitance description conditions symbol typ max units notes control input capacitance c i 3 4 pf 6 input/output capacitance (dq) c o 4 5 pf 6 address capacitance c a 3 3.5 pf 6 clock capacitance c ck 3 3.5 pf 6 t a = 25 o c; f = 1 mhz v dd = 3.3v
sram as5ss128k36 austin semiconductor, inc. as5ss128k36 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 description conditions sym -11 -12 units notes power supply current: operating device selected; all inputs < v il or > v ih ; cycle time > t kc (min) v dd = max; outputs open i dd 275 250 ma 1, 2 power supply current: idle device selected; v dd = max; cke\ > v ih ; all inputs < v ss + 0.2 or > v dd -0.2; cycle time > t kc (min) i dd1 22 20 ma 1, 2 cmos standby device selected; v dd = max; all inputs < v ss + 0.2 or > v dd -0.2; all inputs static; clk frequency = 0 i sb2 10 10 ma 2 ttl standby device selected; v dd = max; all inputs < v il or > v ih ; all inputs static; clk frequency = 0 i sb3 25 25 ma 2 clock running device selected; v dd = max; adv/ld\ > v ih ; all inputs < v ss + 0.2 or > v dd - 0.2; cycle time > t kc (min) i sb4 65 60 ma 2 snooze mode zz > v ih i sb2z 10 10 ma 2 max i dd operating conditions and maximum limits (-55 o c < t a < +125 o c; v dd, v dd q = +3.3v +0.165v unless otherwise noted) thermal resistance description conditions sym typ units notes thermal resistance (junction to ambient) q ja 46 o c/w 3 thermal resistance (junction to top of case) q jc 2.8 o c/w 3 test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51 note: 1. i dd is specified with no output current and increases with faster cycle times. i dd q increases with faster cycle times and greater output loading. 2. device deselected means device is in a deselected cycle as defined in the truth table. device selected means device is active (not in deselected mode). 3. this parameter is sampled.
sram as5ss128k36 austin semiconductor, inc. as5ss128k36 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 description sym min max min max units notes clock clock cycle time t khkh 11 12 ns clock frequency t kf 90 83 mhz clock high time t khkl 3.0 3.0 ns 1 clock low time t klkh 3.0 3.0 ns 1 output times clock to output valid t khqv 8.5 9.0 ns clock to output invalid t khqx 3.0 3.0 ns 2 clock to output in low-z t khqx1 3.0 3.0 ns 2, 3, 4, 5 clock to output in high-z t khqz 5.0 5.0 ns 2, 3, 4, 5 oe\ to output valid t glqv 5.0 5.0 ns 6 oe\ to output in low-z t glqx 0 0 ns 2, 3, 4, 5 oe\ to output in high-z t ghqz 5.0 5.0 ns 2, 3, 4, 5 setup times address t avkh 2.2 2.5 ns 7 clock enable (cke\) t evkh 2.2 2.5 ns 7 control signals t cvkh 2.2 2.5 ns 7 data-in t dvkh 2.2 2.5 ns 7 hold times address t khax 0.5 0.5 ns 7 clock enable (cke\) t khex 0.5 0.5 ns 7 control signals t khcx 0.5 0.5 ns 7 data-in t khdx 0.5 0.5 ns 7 -11 -12 ac electrical characteristics 6, 8, 9 (-55 o c < t a < +125 o c; v dd, v dd q = +3.3v +0.165v) note: 1. measured as high above v ih and low below v il . 2. contact asi for more information on these parameters. 3. this parameter is sampled. 4. this parameter is measured with the output loading shown in figure 2. 5. transistion is measured +200mv from steady state voltage. 6. oe\ can be considerted a dont care during writes; however, controlling oe\ can help fine-tune a system for zbl timing. 7. this is a synchrnous device. all addresses must meet the specified setup and hold times for all rising edgges o clk when the y are being registered into the device. all other synchronous inputs must meet the setup and hold times with stable logic levels for all r ising edges of clock (clk) when the chip is enabled. chip enable must be valid at each rising edge of clk when adv/ld\ is low to remain enabl ed. 8. test conditions as specified with the output loading shown in figure 1, unless otherwise noted. 9. a write cycle is defined by r/w\ low having been registered into the device at adv/ld\ low. a read cycle is defined by r/w\ high with adv/ld\ low. both cases must meet setup and hold times.
sram as5ss128k36 austin semiconductor, inc. as5ss128k36 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 11 ac test conditions output loads fig. 2 output load equivalent fig. 1 output load equivalent input pulse levels input timing reference levels input slew rate output reference levels output load vss to 3.3v 1.5v 1 ns 1.5v see figures 1 and 2 3.3v q 351 w 5 pf 317 w q 50 w z 0 =50 w v t = 1.5v load derating curves the asi 128k x 36 zbl sram timing is dependent upon the capacitive loading on the outputs. consult the factory for copies of i/o current versus voltage curves.
sram as5ss128k36 austin semiconductor, inc. as5ss128k36 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 12 snooze mode snooze mode is a low-current, power-down mode in which the device is deselected and current is reduced to i sb2z . the duration of snooze mode is dictated by the length of time the zz pin is in a high state. after the device enters snooze mode, all inputs except zz become dis- abled and all outputs go to high-z. the zz pin is an asynchronous, active high input that causes the device to enter snooze mode. when the zz pin becomes a logic high, i sb2z is guaranteed after the time t zzi is met. any read or write operation pending when the device enters snooze mode is not guaranteed to complete sucessfully. therefore, snooze mode must not be initiated until valid pending operations are completed. similarly, when exiting snooze mode during t rzz , only a deselect or read cycle should be given. snooze mode electrical characteristics description conditions sym min max units notes current during snooze mode zz > v ih i sb2z 10 ma zz active to input ignored t zz 0 t khkh ns 1 zz inactive to input sampled t rzz 0 t khkh ns 1 zz active to snooze current t zzi t khkh ns 1 zz inactive to exit snooze current t rzzi 0ns1 snooze mode waveform clk zz i supply all inputs (except zz) outputs (q) 12345 12345 12345 12345 12345 12345678901234567890 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 12345678901234567890 12 12 12 12 12 12345 12345 12345 12345 12345678901234567890 1 234567890123456789 0 1 234567890123456789 0 12345678901234567890 12 12 12 12 123456 123456 123456 123456 123456 12345 12345 12345 12345 12345 123456789012345678901 1 2345678901234567890 1 1 2345678901234567890 1 1 2345678901234567890 1 123456789012345678901 12 12 12 12 12 12 12 12 12 12 deselect or read only 1 12 t rzz 1 1 t zz 1 1 t zzi i isb2z high-z 1 12 t rzzi 12345 1 234 5 1 234 5 1 234 5 12345 dont care
sram as5ss128k36 austin semiconductor, inc. as5ss128k36 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 13 read/write timing read/write timing parameters min max min max t khkh 11 12 t kf 90 83 t khkl 3.0 3.0 t klkh 3.0 3.0 t khqv 8.5 9.0 t khqx 3.0 3.0 t khqx1 3.0 3.0 t khqz 5.0 5.0 t glqv 5.0 5.0 t glqx 00 symbol -12 -11 min max min max t ghqz 5.0 5.0 t avkh 2.2 2.5 t evkh 2.2 2.5 t cvkh 2.2 2.5 t dvkh 2.2 2.5 t khax 0.5 0.5 t khex 0.5 0.5 t khcx 0.5 0.5 t gldx 0.5 0.5 symbol -12 -11 note: 1. for this waveform, zz is tied low. 2. burst sequence order is determined by mode (0=linear, 1=interleaved). burst operations are optional. 3. ce\ represents three signals. when ce\ = 0, it represents ce\ = 0, ce2\ = 0, ce2 = 1. 4. data coherency is provided for all possible operations. if a read is initiated, the most current data is used. the most recent data may be from the input data register. 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 123 123 123 1234 1234 1234 1234 1234 1234 123 123 123 123 123 123 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 12 12 12 1 1 1 123456789 1 2345678 9 123456789 12 12 12 1 1 1 12 12 12 12 12 12 12345678 1 234567 8 12345678 12 12 12 12 12 12 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 123 123 123 123 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234567890 1234567890 1234567890 1234 1234 1234 1234 1234567890 1234567890 1234567890 1234 1234 1234 1234 1234 1234 1234567890 1234567890 1234567890 1234 1234 1234 1234 1234 1234 1234 1234 1234 1 1 12 12 123456789012345678901 1 2345678901234567890 1 123456789012345678901 12 12 12 12 12 12 12 12 12 12 12345678 1 234567 8 12345678 12 12 12 12 12 12 123456789 123456789 123456789 1234 1234 1234 a1 1234 1234 1234 a2 123 123 123 123 123 123 1234567 1 23456 7 1234567 1 1 1 12 12 12 a3 123 123 123 a4 123 123 123 123 123 123 1234567 1 23456 7 1234567 12 12 12 1 1 1 a5 123 123 123 a6 123 123 123 a7 123 123 123 1234567 1 23456 7 1234567 1 1 1 1234 1234 1234 d(a1) 123 123 123 d(a2) 123 123 123 d(a2+1) 123 123 123 123 q(a3) 12 12 12 12 q(a4) 12 12 12 12 q(a4+1) 123 123 123 123 d(a5) 12 12 12 12 q(a6) 123 123 123 123 123 123 123 123 d(a7) write d(a1) write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4 +1) write d(a5) read q(a6) write d(a7) deselect 123 1 2 3 123 dont care 1234 1 23 4 1 23 4 1234 undefined clk cle\ ce\ adv/ld\ r/w\ bwx\ address dq oe\ command 1 2 3 4 5 6 7 8 9 10 t khkh t khkl t klkh t evkh t khex t cvkh t khcx t avkh t khax t dvkh t khdx t khqx1 t khqv t khqx t ghqz t glqx t glqv t khqx t khqz
sram as5ss128k36 austin semiconductor, inc. as5ss128k36 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 14 nop, stall and deselect cycles 123 123 123 123 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234567890123456 1234567890123456 1234567890123456 1234 1234 1234 1234 12 12 12 12 12 12 1234567890123456789012 1 23456789012345678901 2 1234567890123456789012 12 12 12 12 12 12 12345678901234567890123 12345678901234567890123 12345678901234567890123 a1 a2 a3 123 123 123 a4 123 123 123 123 123 123 12345678901234 1 234567890123 4 12345678901234 1 1 1 12 12 12 a5 123 123 123 12345678901234 1 234567890123 4 12345678901234 1 1 1 123 123 123 d(a1) 1234 1234 1234 1234 q(a2) 123 123 123 123 q(a3) 123 123 123 123 q(a5) 12 12 12 12 write d(a1) read q(a2) stall read q(a3) write d(a4) stall nop read q(a5) deselect continue deselect 123 1 2 3 123 dont care 1234 1 23 4 1 23 4 1234 undefined clk ce\ adv/ld\ r/w\ bwx\ address dq command 1 2 3 4 5 6 7 8 9 10 t khqx t khqz 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 123 123 123 123 1234 1234 1234 1234 123 123 123 123 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 cke\ 1234 1234 1234 1234 1234 1234 1234 1234 1234 1 1 12 12 12345678 1 234567 8 12345678 12 12 12 12 12 123 123 123 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 12 12 12 12 12 12 12345678 1 234567 8 12345678 12 12 12 12 12 12 1 1 1 12 12 12 123456789 1 2345678 9 123456789 12 12 12 12 12 12 123 123 123 123 1234 1234 1234 1234 1234 1234 1234 123456789 123456789 12 12 12 12 12345678 1 234567 8 12345678 12 12 12 12 12 12 12 12 12 12 12 12 12345678 1 234567 8 12345678 12 12 12 12 12 12 1 1 1 12 12 12 123456789 1 2345678 9 123456789 1 1 1 12 12 12 1234567890 1234567890 1234567890 12 12 12 12 d(a4) nop, stall and deselect timing parameters min max min max t khqx 3.0 3.0 t khqz 5.0 5.0 symbol -12 -11 note: 1. the ignore clock edge or stall cycle (clock 3) illustrates cke\ being used to create a pause. a write is not performed during this cycle. 2. for this waveform, zz and oe\ are tied low. 3. ce\ represents three signals. when ce\ = 0, it represents ce\ = 0, ce2\ = 0, ce2 = 1. 4. data coherency is provided for all possible operations. if a read is initiated, the most current data is used. the most rec ent data may be from the input data register.
sram as5ss128k36 austin semiconductor, inc. as5ss128k36 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 15 asi case # 1001 (package designator dq) note: all dimensions in millimeters. detail a 1.40 + 0.05 0.10+0.10/-0.05 1.00 typ 0.60 + 0.15 0.32+0.06/-0.10 0.65 basic 1.50 + 0.10 see detail a 0.15 +0.03/-0.02 16.00 +0.20/-0.05 14.00 + 0.10 22.10 +0.10/-0.15 20.10 + 0.10
sram as5ss128k36 austin semiconductor, inc. as5ss128k36 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 16 ordering information *available processes it = industrial temperature range -40 o c to +85 o c xt = extended temperature range -55 o c to +125 o c example: as5ss128k36dq-11/it device number package type speed ns process as5ss128k36 dq -11 /* as5ss128k36 dq -12 /*

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